The present invention relates to amplifiers used to provide digital data to electric lines, and more specifically to amplifiers providing data in parallel on several lines.
Data transmitted in parallel by means of several lines are frequently used in digital circuits. Each line receives the signals provided by a buffer amplifier, and behaves as a capacitive load of this amplifier. A logic signal provided by a buffer amplifier to a capacitive load exhibits transitions having a slope which is steeper as the load capacitance is small. A logic signal is taken into account when it reaches a switching voltage threshold, this threshold being reached all the faster as the signal has transitions of steep slope.
Considering several buffer amplifiers concurrently providing respective logic signals to identical logic gates via lines having different capacitances, the logic gates take account of the signal transitions at different times.
In some applications, it may be necessary to guarantee that the signals provided at the same time are taken into account practically at the same time by the logic gates.
The capacitance of a line mainly depends on its dimensions. When a parallel bus including many lines is designed on a circuit, the lengths of each bus line is generally, for routing reasons, very different from the others, although they start from a same circuit node and end at a same circuit node. It is difficult to design a parallel bus and give the same dimensions to all bus lines. Rather than adjusting the value of the load of each buffer amplifier, the size of each amplifier may also be adjusted, according to its load. Such adjustments are complex, lengthy and of expensive implementation.
The received data may also be resynchronized, for example, by installing a D flip-flop at the end of each line and by synchronizing all flip-flops on a same synchronization signal. However, such a solution implies that the frequency of the used synchronization signal be equal to the frequency of the data signals or equal to a multiple of this frequency. If, as frequently occurs, no frequency greater than the data signal frequency is available on the circuit, one period of the data frequency passes between the data transmission over the electric lines and their resynchronization, at the output of the D flip-flops.
In some circuits, especially memory circuits, such a synchronization delay can be too high to reach a desired operating rate.
An aspect of the present invention is to provide a device enabling resynchronization of the data transmitted in parallel.
According to this aspect, the present invention provides an amplifier having a fan-out which varies according to the time spent between an edge of a synchronization signal and an edge of a logic input signal.
According to an aspect of the present invention, the amplifier includes several identical blocks, each including an output stage connected between a data input and a data output, the data input and output being respectively connected to the data inputs and outputs of the other blocks, a delay element, the delay elements of all blocks being connected in series, the delay element of the first block receiving the synchronization signal, an edge detector, the input of which is connected to the input of the output stage, and means for inhibiting the propagation of the synchronization signal through the delay element when the signal generated by the edge detector of the preceding block is active and for activating the output stage and the edge detector when the signal generated by the delay element of the preceding block is active.
According to an aspect of the present invention, the amplifier includes several identical blocks, each including an output stage connected between a data input and a data output, the data input and output being respectively connected to the data inputs and outputs of the other blocks, a delay element, the delay elements of all blocks being connected in series, the delay element of the first block receiving the synchronization signal, an edge detector, the input of which is connected to the input of the output stage, and means for inhibiting the propagation of the synchronization signal through the delay element when the signal generated by the edge detector of the preceding block is active and for inhibiting the output stage and the edge detector when the signal generated by the delay element of the preceding block is active.
According to an aspect of the present invention, each of the blocks includes a first MOS transistor of a first conductivity type connected between a first supply terminal and a data output terminal, and connected in series between a synchronization terminal and the synchronization terminal of the next block, a first inverter supplied between the first supply terminal and a second supply terminal via a second MOS transistor of the second conductivity type, a second inverter, and a delay element, the gate of the first transistor being connected to the gate of the second transistor of the next block, and being activated when both a data input signal and the signal provided to the synchronization terminal of the next block are activated.
According to an aspect of the present invention, the second inverter is connected at the output of the first inverter, and the delay element includes an adjustable current source between the second transistor and the second supply terminal, and a third inverter and a capacitor, series-connected between the output of the second inverter and the connection between the second transistor and the first inverter.
According to an aspect of the present invention, the current source is set to provide a decreasing current when the intrinsic conductivity of the transistors increases.